Examining the Impact of ACE interference on Multi-Bit AVF Estimates

Until recently, soft error reliability has been focused on single-bit errors and as a consequence, methodologies for Architectural Vulnerability Factor (AVF) analysis have been well defined and established for single-bit faults. However, studies have shown that multi-bit faults are becoming more prevalent with technology scaling [1]. If this trend continues, multi-bit faults will eventually become a high percentage of all microprocessor faults. Research into modeling methodologies for multi-bit faults is scarce. Recently, we presented an Architecturally Correct Execution (ACE) analysis methodology to evaluate the AVF of spatial multi-bit faults (MB-AVF) [2]. We used our methodology to study multi-bit AVF by extending the ACE analysis infrastructure of a performance simulator. While this methodology precisely measures AVF for Detected Unrecoverable Errors (DUEs), it only approximates AVF for Silent Data Corruptions (SDC). This is because the methodology determines a bit’s ACE state using a single-bit ACE analysis. However, a bit’s ACE state may change due to the presence of another bit flip, a condition termed ACE interference, and this effect will not be captured by the MB-AVF modeling methodology. As a result, our SDC calculation method is accurate only if ACE interference is rare for multi-bit faults. In this paper, we present a fault injection study to determine the prevalence of ACE interference in typical benchmarks executing on a GPU. Our results show that ACE interference is a rare event in GPUs: we found that the ACE state of a bit rarely changes in presence of other faults. These results support the conclusion that our multi-bit ACE analysis can accurately estimate the SDC AVF of a processor design.